## Tuesday, October 30, 2012

### simple make example

• You can use variable by assigning it, and use it with $(), it can be anything, you can even think of it as a macro. • You can use$@ to replace the target. @ is a good name to represent the goal(target).
• $+ means all prerequisites with space separated when multiple is given. • %.o:%.c shows the relationship based on extension name. Don't forget it uses % not *. # 1 # Defining the compiler: CC=gcc # Defining the object files: objects = main.o example.o # 2 # The default rule - compiling our main program: all: sample echo all: make complete # 3 sample:$(objects)
# If we get here, all the dependencies are now built.
$(CC) -o$@ $+ # 4 # Tell make how to build .o files from .c files: %.o:%.c$(CC) -c \$+